The present invention relates generally to processes for manufacturing insulated-gate power semiconductor devices such as MOSFETs, as well as other more complex devices including MOSFET-like structures, such as Insulated Gate Rectifiers and MOS-gated Thyristors. The invention more particularly relates to such processes resulting in minimal cell size devices, characterized by involving a minimal number of photolithographic masking steps, by having self-aligned source-base shorts, thereby reducing the minimum cell size, and by being fail-safe in a number of respects so as to provide a relatively high process yield.
Known power MOSFETs generally comprise a multiplicity of individual unit cells (sometimes numbering in the thousands) formed on a single silicon semiconductor wafer in the order of 300 mils (0.3 in.) square in size and electrically connected in parallel. Each cell is typically about thirty microns in width. A number of geometric arrangements for the unit cells are possible, including elongated strips.
One particular known process for manufacturing power MOSFETs is a double diffusion technique which begins with a common drain region of, for example, N conductivity type semiconductor material, in turn formed on an N+ conductivity type substrate. Specifically, within the drain region a base region is formed by means of a first diffusion to introduce impurities of one type and then a source region is formed entirely within the base region by means of a second diffusion to introduce impurities of opposite type. If the drain region is N type, then the first diffusion is done with acceptor impurities to produce a P type base region, and the second diffusion is done with donor impurities to produce an N+ type source region. At the drain region surface, the base region exists as a band between the source and drain regions.
Conductive polysilicon gate electrodes are formed on the surface over the base region band and separated by a gate insulating layer. When voltage of proper polarity is applied to the gate electrodes during operation, an electric field extends through the gate insulating layer into the base region forming a conductive channel just under the surface. Current flows horizontally between the source and drain region through the conductive channel.
To form the gate insulating layer and gate electrode structure, during initial wafer preparation a uniform gate insulating oxide layer and then a uniform layer of highly-doped polysilicon are grown over the drain region, prior to any introduction of impurities to form the base and source regions. Channels are then etched through the polysilicon layer and the gate insulating oxide to define the polysilicon electrodes spaced along the drain region.
In a power MOSFET structure, the source, base and drain regions correspond respectively to the emitter, base and collector of a parasitic bipolar transistor. As is known, if this parasitic bipolar transistor is allowed to turn on during operation of the power MOSFET, the blocking voltage and the dV/dt rating of the power MOSFET are substantially degraded. Accordingly, in order to prevent the turn on of the parasitic bipolar transistor during operation of the power MOSFET, the layers comprising the source and base regions are normally shorted together by means of an ohmic connection.
This same general MOSFET structure can be included in other, more complex devices. For example, rather than an N+ conductivity type substrate, a P+ conductivity type substrate may be employed, which becomes the anode region of an Insulated Gate Rectifier (IGR). The previous N conductivity-type drain region is formed as before, but is more generally termed herein a "first region", while the P+ conductivity type anode is herein termed a "second region". The P conductivity-type base region is formed as before in the first region, and the N+ conductivity-type region is formed in the base region. In the case of an IGR, this latter N+ conductivity type region is not termed a source region as before, but rather is a rectifier cathode region or, more generally, an upper electrode region.
As another example, a third device region, of N+ conductivity type, may be provided below the more lightly doped type second region to form the lower main electrode region of an MOS-gated thyristor.
In all of these cases, it will be appreciated that the MOS gate structure is essentially identical, and that the only substantial variations in the overall device structure are in the layers below the first region. In all cases, a short between the upper electrode region (whether it is termed a MOSFET source, an IGR cathode, or a MOS-gated thyristor) and the base region is desired. In all cases, device terminal metallization is connected to the upper electrode region and the gate electrodes.
For convenience, the invention is described herein primarily in the context of a MOSFET. However, it will be appreciated in view of the foregoing that the invention is equally applicable to various other insulated-gate semiconductor devices.
Known power MOSFET designs in manufacture typically require five to seven masking steps, some of which must be aligned to each other with high accuracy to produce working devices. In particular, to form the source-base short, between the first and second diffusion steps a diffusion barrier is applied by means of selective masking over a portion of the base diffusion surface area to prevent the subsequent source diffusion from entering the base diffusion in the area. Thereafter, metallization is applied for the source electrode, and a portion of the source metallization also makes ohmic contact with the previously masked area of the base region.
The large number of masking steps and need for alignment in the prior art processes decrease the process yield. Further, due to the need to provide tolerance for misalignment, unit cell size is larger than would otherwise be needed, undesirably increasing spreading resistance effects. Additionally, prior art process generally provide encased gate electrode structures having remote gate electrode contacts, thus increasing the gate input impedance.